• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A method is provided to enhance the characteristics and reliability of a device with inspection and prevention of a process accident by inspecting whether a process is normal or abnormal through a comparison of values. CONSTITUTION: Plural n+ source/drain regions(19, 21, 23, 25) are formed with implanting n+impurity by using a n+ implant mask on the upper portion of a semiconductor substrate having an n well(13) and a p well(15). Plural p+ source/drain regions(31, 33, 35) are formed with implanting p+ impurity by using a p+ implant mask on the upper portion of the semiconductor substrate. The n+ source/drain regions(19, 21, 23, 25) on the p well(15) has the characteristics of an NPN bipolar device, and p+ source/drain regions(31, 33, 35) on the n well(13) has the characteristics of a PNP bipolar device.
    公开号:KR20000027788A
    申请号:KR1019980045814
    申请日:1998-10-29
    公开日:2000-05-15
    发明作者:박진요
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    Manufacturing method of inspection device for inspecting abnormality of implant
    The present invention relates to a method for manufacturing an inspection apparatus for inspecting abnormalities of an implant, and more particularly, to an inspection apparatus for inspecting an abnormality of a process after an implant process.
    As the semiconductor devices become more integrated, the gate electrodes of the MOS FETs also decrease in width, but when the width of the gate electrodes decreases by N times, the electrical resistance of the gate electrodes increases by N times, which reduces the operating speed of the semiconductor devices. Therefore, in order to reduce the resistance of the gate electrode, polyside, which is a laminated structure of the polysilicon layer and the silicide, is used as the low resistance gate by using the property of the polysilicon layer / oxide layer interface showing the most stable MOSFET characteristics.
    In general, a pn junction formed of a p or n type semiconductor substrate with n or p type impurities is implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region. Therefore, in a semiconductor device having a reduced channel width, the junction depth should be shallow to prevent short channel effects due to side diffusion from the diffusion region, and to prevent junction breakage due to electric field concentration to the drain. For this purpose, there are methods such as forming a source / drain region into an LDD structure.
    However, the implant process, unlike other processes, can not confirm the abnormality of the process progress because no step occurs after the process progress, and therefore the abnormality in the progress of the process is impossible to search and analyze.
    The present invention is to solve the problems of the prior art, by forming a test device for the implant process while performing the manufacturing process of the semiconductor device to detect and analyze the abnormality of the process progress to reduce the yield and reliability of the device It is an object of the present invention to provide a method of manufacturing an inspection apparatus for inspecting an abnormality of an implant to prevent it.
    1 to 5 are cross-sectional views showing a manufacturing method of the inspection device for inspecting the abnormality of the implant according to the present invention.
    <Description of Signs of Major Parts of Drawings>
    11: semiconductor substrate 13: n well
    15: p well 17: n + implant mask
    19, 21, 23, 25: n + source / drain region 27: p + implant mask
    29, 31, 33, 35: p + source / drain region 37: planarization film
    39: metal pad
    In order to achieve the above object, the manufacturing method of the inspection apparatus according to the present invention,
    In the manufacturing method of the inspection apparatus for inspecting the abnormality of the implant process,
    forming an n + source / drain region by implanting n + impurities using an n + implant mask on a semiconductor substrate having n wells and p wells,
    And forming a p + source / drain region by implanting p + impurities using a p + implant mask on the semiconductor substrate.
    Hereinafter, with reference to the accompanying drawings will be described in detail according to the present invention.
    1 to 5 are cross-sectional views showing the manufacturing method of the inspection apparatus for inspecting the abnormality of the implant according to the present invention.
    First, the n well 13 is formed on an p-type or n-type semiconductor substrate 11 by an implant process using an n-well mask (not shown), and the p-well 15 by an implant process using a p-well mask (not shown). ).
    Next, an n + implant mask 17 is formed on the semiconductor substrate 11 to expose a predetermined portion of the n + source / drain region, and the n + impurity is implanted to n + source / drain regions 19, 21, 23, and 25. ). At this time, the n + impurity uses phosphorus (P), arsenic (As) and the like which are pentavalent elements. (See Fig. 1)
    Next, the n + implant mask 17 is removed.
    After measuring the electrical characteristics after the process results are as follows.
    In the case where the n + impurity is implanted normally, the n well 13 and the n + source / drain regions 19 and 21 on the n well 13 are formed by implanting the same pentavalent impurity. The n + source / drain regions 23 and 25 on the p well 15 exhibit characteristics of NPN bipolar devices.
    After the n + implant mask 17 is formed on the semiconductor substrate 11 and the n + impurity is not implanted, n + impurity is implanted into the n + source / drain regions 19, 21, 23, and 25. As a result, the ohmic contact does not occur during the electrical property inspection, resulting in diode characteristics.
    In addition, when n + impurities are implanted on the entire surface of the semiconductor substrate 11 without forming the n + implant mask 17, the n + source / drain regions 23 and 25 on the p well 15 have n + resistance characteristics. Indicates. (See Fig. 2)
    Next, a p + implant mask 27 is formed on the semiconductor substrate 11 to expose a predetermined portion as a p + source / drain region, and p + impurities are implanted to form p + source / drain regions 29, 31, 33, and 35. ). In this case, as the p + impurity, boron (B), boron fluoride (BF 2 ), and the like, which are trivalent elements, are used. (See Fig. 3)
    Next, the p + implant mask 27 is removed.
    After measuring the electrical characteristics after the process results are as follows.
    When the p + impurity is implanted normally, the p + source 15 and the p + source / drain regions 29 and 31 on the pwell 15 are formed by implanting the same trivalent impurity, and thus exhibit electrical characteristics to conduct with each other. The p + source / drain regions 33 and 35 on the n well 13 exhibit characteristics of PNP bipolar devices.
    After the p + implant mask 27 is formed on the semiconductor substrate 11, the p + impurity is implanted into the p + source / drain regions 29, 31, 33, and 35 when the p + impurity is not implanted. As a result, the ohmic contact does not occur during the electrical property inspection, resulting in diode characteristics.
    In addition, when p + impurities are implanted on the entire surface of the semiconductor substrate 11 without forming the p + implant mask 27, the p + source / drain regions 33 and 35 on the n well 13 have p + resistance characteristics. Indicates. (See Fig. 4)
    Next, an interlayer insulating film 37 is formed on the semiconductor substrate 11, and the n + source / drain regions 19, 21, 23, and 25 and p + source / drain regions 29, 31, 33, and 35 are formed. A photoresist pattern (not shown) exposing the light emitting layer is formed, and the interlayer insulating layer 37 is etched using the photoresist pattern as an etching mask to form a metal wiring contact hole (not shown).
    Next, a metal layer (not shown) is formed on the interlayer insulating layer 37 to fill the metal wiring contact hole, and then a metal pad 39 is formed by an etching process using a metal wiring mask. The metal pad 39 is formed by a first metal wiring process during the manufacturing process of a semiconductor device, and is formed to reduce an error due to contact resistance when measuring electrical characteristics and to measure the device in a short time. (See Fig. 5)
    In the manufacturing method of the inspection apparatus for inspecting the abnormality of the implant according to the present invention, while performing the manufacturing process of the semiconductor device, by separately forming an inspection apparatus for inspecting the abnormality by the implant process, the process proceeds to the By measuring the electrical characteristics and deriving the abnormality of the process progress by comparing the prescribed value and the measured value, there is an advantage to improve the yield and productivity by improving the characteristics and reliability of the device by early detection and prevention of process accidents.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] In the manufacturing method of the inspection apparatus for inspecting the abnormality of the implant,
    forming an n + source / drain region by implanting n + impurities using an n + implant mask on a semiconductor substrate having n wells and p wells,
    And forming a p + source / drain region by implanting p + impurities using a p + implant mask on an upper portion of the semiconductor substrate.
    [2" claim-type="Currently amended] The method of claim 1,
    And n + source / drain regions on the p-well have characteristics of NPN bipolar elements.
    [3" claim-type="Currently amended] The method of claim 1,
    And p + source / drain regions on the n well have characteristics of PNP bipolar devices.
    [4" claim-type="Currently amended] The method of claim 1,
    And forming a metal pad in the n + source / drain region and the p + source / drain region to reduce contact resistance.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-10-29|Application filed by 김영환, 현대전자산업 주식회사
    1998-10-29|Priority to KR1019980045814A
    2000-05-15|Publication of KR20000027788A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980045814A|KR20000027788A|1998-10-29|1998-10-29|Method fr manufacturing an inspection apparatus for inspecting an abnormal implant|
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